Low noise amplifier including a single-ended input

ABSTRACT

A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of and claims priority to U.S.application Ser. No. 12/824,927 filed on Jun. 28, 2010 and entitled “LNACircuit for Use in a Low-Cost Receiver Circuit,” which issued on Aug.14, 2012 as U.S. Pat. No. 8,242,844, and which is incorporated herein byreference in its entirety.

FIELD

The present disclosure is generally related to amplifiers, and moreparticularly, to low noise amplifiers (LNAs).

BACKGROUND

Commercial television receivers and set-top boxes supporting variousdigital television standards require tuner circuitry capable ofprocessing analog terrestrial, digital terrestrial, and cable broadcastswith low cost and small size. Such tuner circuitry may be configured tohandle signals with broadband input frequencies ranging from 54 MHz to880 MHz, and thus require a wideband LNA with sufficiently highlinearity and a low noise figure well below 3 dB in order to obtain highsensitivity.

Narrow-band receivers, such as Code-Division Multiple Access (CDMA),Global System for Mobile Communications (GSM), short-range wirelessreceivers, and terrestrial digital multimedia broadcasting (T-DMB)receivers, are typically configured to tune to channels where the ratioof maximum frequency to minimum frequency is less than two. Unlike suchnarrow-band receivers, in a hybrid television tuner, the second andthird-order input-referred intercept points (IIP2 and IIP3) of the LNAare important. The IIP2 and IIP3 of the LNA are important because, inthe frequency band of reception (54 MHz to 880 MHz), there can be aninterfering channel with a frequency that is half or a third of thedesired frequency channel, which interfering channel, through secondorder or third order distortion, respectively, can land at the frequencyof interest and corrupt the picture quality. Such second or third orderdistortion products are called HD2 (harmonic distortion 2) and HD3(harmonic distortion 3), respectively.

Furthermore, in a cable TV environment, there can be several channelsdistributed over the frequency band of reception. These channels caninter-modulate amongst themselves through second order nonlinearitiesand corrupt the desired picture quality through composite second orderdistortion (CSO). Furthermore, in the presence of third ordernonlinearities in a cable TV tuner, the TV channels can inter-modulateto produce a composite triple beat (CTB) which can further affect thedesired picture quality. Hence, it is important that an LNA in a TVtuner has high IIP2 and IIP3. Therefore, since an LNA with asingle-ended input and single-ended output typically has poor IIP2performance, many tuners adopt a balun together with a fullydifferential LNA or a single-ended-to-differential amplifier as thefirst stage of the receiver circuit.

While fully differential LNAs can provide acceptable IIP2 performanceover a wide range of frequencies, one of its main drawbacks is thatpassive transformers are typically required to convert the single-endedsignal into a differential signal. Such transformers can be bulky;therefore, such transformers are generally implemented off-chip.Further, low-loss, external, passive transformers are typicallyexpensive, adding to the overall cost of the system. Furthermore, theloss in these external transformers directly affects the Noise Figure(NF) of the TV tuner, which is one of the most important performancemetrics of a TV tuner because the NF determines how small of a broadcastTV signal can be received at the antenna input.

A single-ended-to-differential amplifier represents a good configurationfor integration and can provide moderate IIP2 performance. However,conventional single-ended-to-differential amplifiers typically have arelatively high NF. Unfortunately, the high NF degrades sensitivity ofthe tuner circuitry, making it difficult to use an LNA on the firststage in a wideband tuner.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial block and partial schematic diagram of aconventional, single-ended input, differential output, low-noiseamplifier (LNA) with a balanced load.

FIG. 2 is a partial block and partial schematic diagram of aconventional, differential-input, differential output, LNA with abalanced load and a balun circuit.

FIG. 3 is a partial block and partial schematic diagram of a balunlessLNA circuit configurable for use with a tuner circuit.

FIG. 4 is a block diagram of an embodiment of a device including the LNAcircuit of FIG. 3.

FIG. 5 is a diagram of another embodiment of a device including the LNAcircuit of FIG. 3 coupled to a passive mixer.

FIG. 6 is a diagram of still another embodiment of a device includingthe LNA of FIG. 3 coupled to a mixer through a resistive load.

In the following description, the use of the same reference numerals indifferent drawings indicates similar or identical items.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

An embodiment of a low-noise amplifier (LNA) is described below that isconfigured to achieve a second-order input-referred intercept point(IIP2) of greater than 50 dBm (dB milliwatts) while eliminating thebalun and while reducing power consumption of the LNA by three-fourthsas compared to a conventional LNA.

In the following discussion, the term “coupled” is used to refer tocomponents that are directly connected or are joined or linked byindirect connection. It should understood that the illustratedembodiments are for illustrative purposes only, and that directconnections illustrated within the drawings may include elements and/orintervening components that are not shown.

FIG. 1 is a partial block and partial schematic diagram of aconventional, single-input, differential-output low-noise amplifier(LNA) circuit 100 with a balanced load. LNA circuit 100 includes a LNA102, which is coupled to a signal source 104 and to a load circuit 106.Load circuit 106 can be a tuner, switches of a mixer, or othercircuitry. Signal source 104 can be an antenna or other circuitry forreceiving a broadband signal. Signal source 104 models an antenna as avoltage source 108 that applies a signal to a resistance 110, such as a75 Ohm resistor. The resistor 110 is coupled to a pin 112 of LNA 102.

LNA 102 includes pin 112 and a second pin 114, which is coupled toground. LNA 102 further includes resistors 116 and 118, transistors 126and 128, and capacitors 120 and 122. Resistor 116 has a first terminalcoupled to pin 112 and a second terminal coupled to a source of atransistor 126, which is an n-channel metal oxide semiconductor fieldeffect transistor (NMOSFET). Transistor 126 includes a gate coupled topin 114 through capacitor 114, and a drain coupled to balanced loadcircuit 106. Resistor 118 includes a first terminal coupled to pin 114and a second terminal coupled to a source of transistor 128. Transistor128 further includes a gate coupled to pin 112 through capacitor 122 anda drain coupled to balanced load circuit 106. In this example,transistors 126 and 128, capacitors 120 and 122, and resistors 116 and118 are substantially matched, providing a balanced circuit.

In operation, signal source 104 provides radio frequency (RF) signals topin 112, and pin 114 is coupled to ground. The RF input at pin 112 isapplied to transistor 126 and resistor 116 and is provided to the gateof transistor 128. Small signal (high frequency) current (i) flows fromdrain to source through transistor 126 and from source to drain throughtransistor 128. For a given voltage signal source (Vs), the current (i)is the same through both transistors 126 and 128. Thus, a differentialoutput current is produced from a single ended voltage input. As usedherein, the term “radio frequency” refers to a signal having a frequencywithin a range from approximately 3 kHz to hundreds of Gigahertz. Highfrequency signals or small signals refer to AC components or RFcomponents of the signal.

Analysis indicates that an optimal noise figure is obtained according tothe following equation:

$\begin{matrix}{{50\Omega} \approx {R + \frac{1}{gm}}} & (1)\end{matrix}$

In Equation 1, the variable (R) represents the resistance of each of theresistors 116 and 118 and the variable (gm) represents thetransconductance of each of transistors 126 and 128. In this instance,an optimized noise figure of LNA 102 is as high as 6 dB. However, thenoise figure of 6 dB is not acceptable for terrestrial applications.Further, the IIP2 was only 40 dBm (the power ratio referenced to onemilliwatt), which is insufficient for cable applications for which 50dBm is a typical threshold. Unfortunately, the common source stagerepresented by transistor 128 contributes significant noise to thesignal, adversely affecting the noise figure (NF) and sensitivity of thesystem while giving insufficient IIP2 performance.

While a single-ended input avoids the use of external and bulky passivetransformers, due to the relatively high noise figure, it is difficultto place LNA 102 on the first stage in a wideband tuner due to theresulting sensitivity degradation. Conventionally, a balun circuit, suchas an external transformer, is used to convert the single-ended inputinto a differential input through electromagnetic coupling. An exampleof an LNA circuit that uses a balun circuit is described below withrespect to FIG. 2.

FIG. 2 is a partial block and partial schematic diagram of aconventional, dual-input LNA circuit 200, including the LNA 102 of FIG.1 and including a balun circuit 206. In this example, signal source 104is replaced with a signal source 204 that includes balun circuit 206(depicted as a simple transformer). Further, the voltage signal source(Vs) 108 depicted in FIG. 1 is divided into input sources 208 and 210,each of which are approximately half of the voltage signal source (Vs),i.e., Vs/2. Signal source 204 includes resistors 212 and 214, each ofwhich is approximately 37.5Ω or half of the resistance of resistor 110in FIG. 1.

In operation, signal source 204 divides the balanced, single-ended inputsignal (which may be received from an antenna or other signal source)into an unbalanced signal using passive transformer 206 as a balun, andprovides the resulting signals to LNA 102 at pins 112 and 114. The smallsignal voltages appear across transistor 126 and 128, causing smallsignal current (i) to flow from drain to source through transistor 126and from source to drain through transistor 128, as shown.

Diagram 200 further includes an equivalent circuit 220 illustrating theeffective impedance 222 of LNA circuit 202. In this instance, theeffective impedance of LNA 102 is determined from the resistance ofresistors 116 and 128 plus one over the transconductance (gm) oftransistors 126 and 128, which is approximately 25Ω. The effectiveimpedance is defined by Equation 2 below.

$\begin{matrix}{{25\Omega} \approx {R + \frac{1}{gm}}} & (2)\end{matrix}$

For a given voltage signal source (Vs), the small signal current (i)flowing in both networks is the same. Further, the voltage across theeffective 25Ω resistance is approximately the same as the voltage acrossthe transconductor.

In the illustrated embodiment of FIG. 2, the noise figure is dominatedby the 25Ω impedance. While the fully differential LNA illustrated inFIG. 2 can provide excellent IIP2 performance over a wide frequencyband, a drawback of circuit 200 is that the passive transformer 206 isrequired. Such a passive transformer is typically too bulky to beintegrated on the chip, and its insertion loss degrades the receiver'snoise figure and its sensitivity. To avoid such degradation, low-lossand expensive external transformers are used, increasing both the sizeand expense of the circuitry. As discussed below with respect to FIGS.3-8, it is possible to provide a single-input, balunless LNA thatobtains a noise figure, IIP2, IIP3, gain, and sensitivity that issufficient for use with terrestrial applications, with reduced powerconsumption and reduced cost.

FIG. 3 is a partial block and partial schematic diagram of an embodimentof a circuit 300 including a single-input, balunless LNA 302configurable for use with a tuner circuit. Circuit 300 includes a signalsource, such as an antenna, a broadband connection, or other signalsource. In this instance, the signal source is represented by voltagesignal source (Vs) 112, which provides RF signals to LNA 302. Thevoltage signal source (Vs) 112 is capacitively coupled to inputs 112 and114 through capacitors 304 and 306, respectively, which operate to blockdirect current and low frequency signals.

As compared to circuit 200 in FIG. 2, the cross-coupling capacitors 120and 122 have been removed, and half of the transconductor is folded top-channel metal oxide semiconductor (PMOS) transistors 312 and 314. LNA302 includes a direct current (DC) current source, represented byinductor 308 coupled to a regulated supply voltage (Vreg). Inductor 308is coupled to pin 112 for injecting a DC current (I_(dc)) into the pin112. LNA 302 further includes a resistor 310 having a first terminalcoupled to pin 112 and a second terminal coupled to a source oftransistor 312, which includes a gate coupled to bias circuitry 311, anda drain coupled to a source of transistor 314. Transistor 314 furtherincludes a gate coupled to bias circuitry 311 and a drain coupled to anoutput node 321. The gates of transistors 312 and 314 appropriatelybiased by bias circuitry 311 to permit the DC current (I_(dc)) to flowthrough transistors 312 and 314. From a RF signal point of view, thegates of transistors 312 and 314 can be thought of as being at ground.

LNA 302 further includes an NMOS transistor 316 including a draincoupled to output node 321, a gate coupled to bias circuitry 311, and asource coupled to a drain of NMOS transistor 318, which also includes agate coupled to bias circuitry 311 and a source coupled to pin 114through resistor 320. A second current source, represented by inductor313, couples pin 114 to a supply terminal, which may be negative supplyterminal or which may include other circuitry. Capacitor 306 blocks DCcurrent flow to voltage signal source (Vs) 108, forcing the DC current(I_(dc)) into inductor 313.

In the illustrated embodiments, details of bias circuitry 311 areomitted for the sake of simplicity. However, any biasing circuitry,including operational amplifiers, control circuits, voltage dividercircuits, or other appropriate circuitry can be used to bias transistors312, 314, 316 and 318 sufficiently to allow current flow through thetransistors.

In the illustrated embodiment, output node 321 is coupled to a mixer.The inductor 322 and variable capacitor 324 form a tunable band-pass LCfilter, also known as a tracking filter. Fixed capacitor 328 andvariable capacitor 326 form a capacitive attenuator network that is usedto reduce the gain prior to the mixer in the presence of strong signals.

Though in the embodiment shown in FIG. 3, the LNA transconductorcomprised of resistors 310 and 320 and transistors 312, 314, 316, and318 is shown coupled to a tracking filter and capacitive attenuatorcomprised of inductor 322 and capacitors 324, 326 and 328, otherembodiments are also possible. For example, the LNA transcondutor couldbe coupled to switches of a passive mixer (as depicted in FIG. 5) or toa simple resistive load (as illustrated in FIG. 6).

In operation, the gates of PMOS transistors 312 and 314 and NMOStransistors 316 and 318 are biased to permit DC current (I_(dc)) toflow. However, the gates of transistors 312, 314, 316, and 318 receiveno small signal currents. The RF input signal (i_(in)) produced byvoltage signal source (Vs) 108 flows through resistor 110 and dividessubstantially evenly to flow into pins 112 and 114. The inductors 313and 308 operate as open circuits with respect to the small signal inputs(i_(in)/2), forcing the small signal inputs (i_(in)/2) to flow throughPMOS transistors 312 and 314 and through NMOS transistors 316 and 318 tooutput node 321, which carries the small signal output current(i_(out)).

In the illustrated embodiment, NMOS transistors 316 and 318 and PMOStransistors 312 and 314 in parallel. Thus, the impedance (Zchip) of theLNA 302 (as seen looking into pins 112 and 114) is determined accordingto the following equation:

$\begin{matrix}{{Zchip} = \left. \left( {{2\; R} + \frac{2}{gm}} \right)||\left( {{2\; R} + \frac{2}{gm}} \right) \right.} & (3)\end{matrix}$

In Equation 3, the resistance (2R) is twice the resistance (R) of theresistors 116 and 118 in circuits 100 and 200 in FIGS. 1 and 2. Thevariable (gm) represents the transconductance of transistors 312 and316. Equation 3 can be simplified as shown in Equation 4 below:

$\begin{matrix}{{Zchip} = {{R + \frac{1}{gm}} = {25\Omega}}} & (4)\end{matrix}$

The equivalent circuit 330 depicts the input resistance 110 and voltagesignal source (Vs) 108 and illustrates the input impedance (Zchip) ofthe LNA 302, which is represented by resistor 332. Thus, the simplifiedcircuit 302 has the same equivalent circuit as the differential circuit200 in FIG. 2.

In the illustrated embodiment, the noise figure is better than thedifferential case. For the differential case (as depicted in FIG. 1),the NF of the trasnconductor can be approximated according to Equation 5below:

$\begin{matrix}{{NF}_{102} = {10*{\log\left( {1 + \frac{Zchip}{2*75}} \right)}}} & (5)\end{matrix}$

For an impedance (Zchip) equal to about 25 ohms, the NF is about 0.7 dB.However, the off-chip balun can have a loss of about 1.3 dB, furtherdegrading the total NF to about 2 dB. In contrast, the single endedtransconductor of FIG. 3 has an NF that can be approximated according tothe Equation 6 below:

$\begin{matrix}{{NF}_{302} = {10*{\log\left( {1 + \frac{Zchip}{75}} \right)}}} & (6)\end{matrix}$

For the same impedance (Zchip) of 25 ohms, the NF of LNA 302 is 1.25 dB.Since an off-chip balun is not used, the total NF is also 1.25 dB, whichis better than the 2 dB NF of the differential case with the balun.Furthermore, for a given voltage signal source (Vs) 108, the smallsignal current (i) flowing into the LNA remains the same as in thedifferential case, and hence gain is also the same.

For the single-ended CMOS transconductor (with NMOS and PMOS devices inparallel) as shown in FIG. 3, LNA 302 is similar to the LNA 102 inFIG. 1. Thus, the third-order input-referred intercept point (IIP3) issubstantially the same as the differential structure depicted in FIG. 2.The IIP3 of LNA 302 is described below with respect to Equation 7.

$\begin{matrix}{{{IIP}\; 3} \propto {{Von} \cdot \left( {1 + {gmR}} \right)^{\frac{3}{2}}}} & (7)\end{matrix}$

Further, the second-order input-referred intercept point (IIP2) is alsoimproved, as compared to the single-end input LNA 102 in FIG. 1. TheIIP2 is improved by using conventional push-pull complementary stages.Second order distortion is characterized by asymmetric positive andnegative half cycles. During the positive half cycle, NMOS transistors316 and 318 have a small “on” voltage (Von), while PMOS has a larger“on” voltage (Von). During the negative half cycle, the opposite istrue. If NMOS and PMOS transistors 312 and 318 match, then the secondorder distortion cancels. However, process variations that cause NMOStransistor 318 to be different from PMOS transistor 312 can cause theIIP2 to change.

The “on” voltages of PMOS and NMOS transistors 312, 314, 316, and 318are opposite, balancing out. Further, using source degenerationresistors 310 and 320 desensitizes the “effective” on voltage (voltageacross resistors plus “on” voltage of transistors) variations acrossprocess corners.

However, testing has shown that LNA 302 has a satisfactory IIP2 acrossprocess corners, which exceeds 50 dBm. Table 1 below depicts the IIP2 ofone specific example of LNA 302 where the PMOS transistors 312 and 314had width/length ratios that were 2.00 times that of NMOS transistors316 and 318.

TABLE 1 IIP2 of LNA 302 across Process Corners. PROCESS CORNER IIP2(dBm) Typical-Typical (TT) 54 Slow NMOS Fast PMOS (SNFP) 61 Fast NMOSSlow PMOS (FNSP) 51 Fast NMOS Fast PMOS (FNFP) 56 Slow NMOS Slow PMOS(SNSP) 53

As shown in Table 2, LNA 302 exceeds 50 dBm at all process corners.Further, trimming devices can be added, which change the ratio PMOS W/Lto NMOS W/L, to fine tune performance. However, even at the 2.00×difference between the PMOS and NMOS devices, performance falls withinthe acceptable range.

Further, the DC current (I_(dc)) is approximately equal to one-fourth ofa differential current (I_(differential)), representing a 4× currentsavings over a conventional LNA. Referring to LNA 102 in FIG. 2, eachNMOS transistor 126 and 128 has a transconductance of gm and eachsingle-ended brand drew a DC current of I_(diff)/2. For the CMOS LNA302, the PMOS and NMOS transistors 312, 314, 316, and 318, eachtransistor 312, 314, 316, and 318 has a transconductance of gm/2 whilesharing the same DC current. This implies that the current drawn isone-quarter of the differential current (I_(diff)) as follows:

$\begin{matrix}{{\frac{1}{2}*\left( \frac{I_{diff}}{2} \right)} = \frac{I_{diff}}{4}} & (8)\end{matrix}$

The resulting current represents a 4× current reduction as compared tothe DC current flowing within LNA 102 in FIG. 2, for example. Thus, LNA302 has noise figure, IIP2, IIP3, and gain parameters that satisfyterrestrial TV signal processing requirements, while using less DCcurrent.

With a single-ended load of 440 Ohms, which matches the differentialload of some LNAs with a balun, Table 2 below represents a simulationperformance summary and comparison of LNA 302 with LNA 102 in FIG. 2,for example, with a corresponding 440 Ohm load, transconductance of NMOSand PMOS being 40 mS each and resistors 310, 320 in FIG. 3 each being 25ohms, the following performance is obtained.

TABLE 2 LNA 302 versus LNA 102 Performance Comparisons. CMOS LNA 302 LNA102 Without Balun with Balun S11 (Input Reflection ~−7 dB ~−6 dBParameter) Noise Figure (@ 400 MHz) 2.6 dB 3.5 dB Gain 18 dB 18 dB IIP2(Typical-Typical) 54 dBm 55 dBm IIP3 (Out of Band) 26 dBm 26 dBm DCPower 9 mA 40 mA

As indicated in Table 2, the CMOS LNA 302 without the balunsubstantially matches performance of the LNA 102 with the balun. The NFof LNA 302 is better than that of LNA 102, while IIP2, IIP3 and Gainnumbers are comparable between the two. Also, DC current drawn by LNA302 is 75% less than that drawn by LNA 102. Performance of the LNA 302across process corners can be adjusted for a particular implementation.In particular, at design time, the width/length (W/L) ratio of PMOS 312and the W/L of NMOS 318 can be designed to optimize the IIP2 performanceacross process corners.

FIG. 4 is a block diagram of a device 400 including the LNA 302 of FIG.3. Device 400 further includes an antenna 402, connector 404, pin 405,and capacitive filter and capacitive attenuator 406, which includes anoutput coupled to a single input to differential output converter 408,which is coupled to a double balanced harmonic rejection mixer (HRM)410.

In this embodiment, the CMOS LNA 302 obtains a noise figure of 2.6 dB, again of 18 dB, and IIP2 of 50 dBm, an IIP3 of 25 dBm, and a DC currentof approximately 10 mA. The single-ended capacitive filter andcapacitive attenuator 406 provides a single-ended transfer function thatprovides the same load as a differential load. The single input todifferential output converter 408 obtains a noise figure of 9 dB, a gainof 0 dB, an IIP3 of 15 dBm, and a DC current of approximately 15 mA. HRM410 obtains a noise figure of 12 dB, a gain of 19 dB, and an IIP3 of 12dBm. In this particular embodiment, the 30 mA current saved by using LNA302 as compared to LNA 102 can be used to provide power to othercircuitry. For example, part of the saved 30 mA can be used in thesingle ended to differential output converter 408 to supply the 15 mA.

It should be understood that the embodiments illustrated in FIGS. 1-4are illustrative only. In the above-examples, the gains, decibel levels,and currents were provided for illustrative purposes. Such values may beappropriate for particular implementations and/or may vary acrossdifferent circuit implementations.

FIG. 5 is a diagram of another embodiment of a device 500 including theLNA circuit 302 of FIG. 3 coupled to a passive mixer 502, which isconfigured to receive the output current (iout) and to produce amulti-phase intermediate frequency (IF) output signal, which can beprovided to other circuitry, such as a filter, an IF amplifier, aprocessor, and/or other circuitry configured to process the IF outputsignal.

While the LNA 302 of FIG. 3 is coupled to a mixer through an LC networkand the LNA 302 of FIG. 5 is coupled to a passive mixer withoutintervening circuitry, other embodiments may include resistive loads orother circuitry between the LNA 302 and the mixer. An example of anembodiment of a device is described below with respect to FIG. 6 thatincludes LNA 302 coupled to a resistive load and a mixer.

FIG. 6 is a diagram of still another embodiment of a device 600including the LNA 302 of FIG. 3 coupled to a mixer through a resistiveload 602. In this example, the resistive load includes a first terminalcoupled to output node 321 and a second terminal coupled to a voltagesource, such as a VMID (a buffered voltage at approximately a midpointbetween a power supply rail and ground).

In general, LNA 302 may be used in a variety of devices to providelow-noise amplification with reduced power consumption (as compared tothe differential LNA 102 of FIG. 1). Further, while LNA 302 has beendepicted with input pins 112 and 114 for receiving the input signalsfrom a signal source, such as antenna 402, it should be understood thatpins 112 and 114 may be eliminated and that a single pin or inputterminal may be used to provide the input signal to capacitors 304 and306, which may be on-chip capacitors.

In conjunction with the circuit 300 depicted in FIG. 3 and the devices400, 500, and 600 depicted in FIGS. 4-6, respectively, together with thetables 1 and 2, a highly linear single-ended, balunless LNA 302 ispresented that achieves an IIP3 of 25 dBm, an IIP2 of 50 dBm (overprocess corners), and a noise figure of 2.6 dB while consuming only 10mA of current. In this instance, the reflection loss achieved is about−6 dB. The LNA lowers costs by eliminating the balun while adding onlyone off-chip inductor and one capacitor to the bill of materials. Thecurrent savings is approximately 30 mA, which current may be used toprovide power to other circuitry, thereby conserving overall powerconsumption.

Although the present invention has been described with reference topreferred embodiments, workers skilled in the art will recognize thatchanges may be made in form and detail without departing from the scopeof the invention.

What is claimed is:
 1. A low-noise amplifier (LNA) comprising: an inputnode configurable to couple to a transmission line to receive an inputsignal; an output node; a first capacitor coupled between the input nodeand a first node; a second capacitor coupled between the input node anda second node; a first resistor coupled to the first node; a secondresistor coupled to the second node; a first transistor including afirst terminal coupled to the first node through the first resistor, acontrol terminal configured to receive a first direct current (DC) biassignal, and a second terminal coupled to the output node; and a secondtransistor including a first terminal coupled to the second node throughthe second resistor, a control terminal configured to receive a secondDC bias signal, and a second terminal coupled to the output node.
 2. TheLNA of claim 1, wherein: the first capacitor includes a first terminalcoupled to the input node and a second terminal coupled to the firstnode; the second capacitor includes a first terminal coupled to theinput node and a second terminal coupled to the second node; and thefirst terminals of the first and second capacitors are coupled to eachother.
 3. The LNA of claim 1, further comprising: a first inductorhaving a first terminal coupled to the first node and a second terminalcoupled to a first DC supply node; and a second inductor including afirst terminal coupled to the second node and a second terminal coupledto a second DC supply node.
 4. The LNA of claim 1, wherein the firsttransistor comprises a p-channel metal oxide semiconductor field effecttransistor (MOSFET) and the second transistor comprises an re-channelMOSFET.
 5. The LNA of claim 4, wherein the first transistor and thesecond transistor are substantially matched and operate as push-pullcomplementary stages that substantially cancel second-order distortion.6. The LNA of claim 1, wherein the first resistor and the secondresistor operate to desensitize on voltage variations between the firstand second transistors across process corners.
 7. The LNA of claim 1,wherein the first node is DC coupled to a first power supply and thesecond node is DC coupled to a second power supply.
 8. A low-noiseamplifier (LNA) comprising: an input node configured to receive an inputsignal from a transmission line; an output node; a first capacitorincluding a first electrode coupled to the input node and a secondelectrode coupled to a first node; a second capacitor including a firstelectrode coupled to the input node and a second electrode coupled to asecond node; a first transistor circuit including a first terminal, acontrol terminal configured to receive a first direct current (DC) biassignal, and a second terminal coupled to the output node; a secondtransistor circuit including a first terminal, a control terminalconfigured to receive a second DC bias signal, and a second terminalcoupled to the output node; a first resistor coupled between the firstnode and the first terminal of the first transistor circuit; and asecond resistor coupled between the second node and the first terminalof the second transistor circuit.
 9. The LNA of claim 8, wherein thefirst transistor circuit comprises a p-channel metal oxide semiconductorfield effect transistor (PMOSFET) circuit and the second transistorcomprises an n-channel metal oxide semiconductor field effect transistor(NMOSFET) circuit.
 10. The LNA circuit of claim 9, wherein the firsttransistor circuit comprises: a first PMOSFET including a source formingthe first terminal of the first transistor circuit, the source coupledto the first node, the first PMOSFET further including a gate and adrain; and a second PMOSFET including a source coupled to the drain ofthe first PMOSFET, a gate, and a drain coupled to the output node. 11.The LNA circuit of claim 10, wherein the second transistor circuitcomprises: a first NMOSFET including a source forming the first terminalof the second transistor circuit, the source coupled to the first node,the first NMOSFET further including a gate and a drain; and a secondNMOSFET including a source coupled to the drain of the first NMOSFET, agate, and a drain coupled to the output node.
 12. The LNA circuit ofclaim 11, further comprising a bias circuit configured to selectivelyprovide the first DC bias signal to the gates of the first and secondPMOSFETs and to selectively provide the second DC bias signal to thegates of the first and second NMOSFETs.
 13. The LNA circuit of claim 8,wherein the first and second transistor circuits have substantiallyequal on voltages and operate as push-pull complementary stages thatsubstantially cancel second-order distortion.
 14. The LNA circuit ofclaim 8, wherein the first and second resistors provide sourcedegeneration for the first and second transistor circuits to reducesensitivity to variations in the on voltages across process corners. 15.A low-noise amplifier (LNA) comprising: a first node that is AC coupledto an input node configured to receive an input signal from atransmission line; a second node that is AC coupled to the input node;an output node; a first resistor including a first terminal coupled tothe first node and including a second terminal; a second resistorincluding a first terminal coupled to the second node and including asecond terminal; a first transistor circuit including a first terminalcoupled to the second terminal of the first resistor, a control terminalconfigured to receive a first direct current (DC) bias signal, and asecond terminal coupled to the output node; and a second transistorcircuit including a first terminal coupled to the second terminal of thesecond resistor, a control terminal configured to receive a second DCbias signal, and a second terminal coupled to the output node; andwherein the first and second transistors operate as push-pullcomplementary stages that substantially cancel second-order distortion.16. The LNA of claim 15, wherein the first resistor and the secondresistor operate to desensitize variations in on voltages between thefirst and second transistors across process corners.
 17. The LNA ofclaim 15, wherein: the first transistor circuit comprises: a firstp-channel metal oxide semiconductor field effect transistor (PMOSFET)including a source forming the first terminal of the first transistorcircuit, the source coupled to the first node, the first PMOSFET furtherincluding a gate and a drain; and a second PMOSFET including a sourcecoupled to the drain of the first PMOSFET, a gate, and a drain coupledto the output node; and the second transistor circuit comprises: a firstn-channel metal oxide semiconductor field effect transistor (NMOSFET)including a source forming the first terminal of the second transistorcircuit, the source coupled to the first node, the first NMOSFET furtherincluding a gate and a drain; and a second NMOSFET including a sourcecoupled to the drain of the first NMOSFET, a gate, and a drain coupledto the output node.
 18. The LNA of claim 17, further comprising a biascircuit coupled to the gates of the first and second PMOSFETs and to thegates of the first and second NMOSFETs.
 19. The LNA of claim 15, furthercomprising: a first inductor having a first terminal coupled to thefirst node and a second terminal coupled to a first DC supply node; anda second inductor including a first terminal coupled to the second nodeand a second terminal coupled to a second DC supply node.
 20. The LNA ofclaim 15, wherein the first node is DC coupled to a first power supplyand the second node is DC coupled to a second power supply.